1. Field of the Invention
The subject invention relates to a semiconductor device and its manufacturing method, especially to a semiconductor device with an L-shape spacer and its manufacturing method.
2. Descriptions of the Related Art
In recent years, high integration flash memories have been used in many industries. One reason is that the reduction of memory cell size significantly decreased the production cost. Conventional shallow trench isolation (“STI”) technologies have often been utilized in the production of flash memories because of the minimized size of the memory cells manufactured thereby and the high integration of the flash memories.
However, a corner thinning effect often occurs in the tunnel insulating layer of the device area of flash memory, lowering the coupling ratio thereby. A lower coupling ratio requires a higher gate voltage to erase the content of the memory, locally generating a high electric field at the edge of the device area and causing serious reliability problems in the devices. Problems include hot-carrier traps, damage to the oxide layers, reduction of write/erase tolerance, read interference, and a decrease of data retention, and thus inhibit the size reduction of flash memory. Moreover, flash memory with a lower coupling ratio generates the Fowler-Nordheim tunneling (“F-N” tunneling) effect at a higher electric field. That is, the electron transporting rate between the floating gate and the source/drain becomes slower, thereby, decreasing the rate of the read/write property. Consequently, when manufacturing semiconductors, it is important to produce a flash memory that has a high coupling ratio without the detriment of the corner thinning effect in the tunnel insulating layer.
Regarding the corner thinning effect of the tunnel insulating layer in the device area, a spacer in the device area of the flash memory device has been proposed. Referring to FIG. 1, the shallow trench isolation structure 11 and the active area 12 are formed onto the substrate 10. To reduce the corner thinning effect, a spacer 13 is formed from the insulating layer on the edge of the active area 12 and at the side of the shallow trench isolation structure 11.
However, the use of the spacer 13 fails to effectively control the coupling ratio. Still referring to FIG. 1, the spacer 13 will reduce the area of the tunnel 15 under the floating gate 14, thus, reducing the channel current between the floating gate 14 and the substrate 10 and slowing down the read/write speed.
Given the above limitations, the semiconductor industry consistently seeks to increase the integration of flash memories without increasing manufacturing costs and avoiding a low coupling ratio to enhance the speed and reliability of the read/write property. Therefore, the subject invention provides a solution that particularly addresses the above problems.